1. Field of the Invention
The present invention relates to a method of manufacturing a thin film transistor.
2. Description of Related Art
Thin film transistors (hereinafter referred to as a “TFT” or “TFTs”) employing, as an active layer, a p-Si film formed on a transparent insulating substrate are being developed as pixel drive elements in active matrix type LCDs (Liquid Crystal Displays).
Poly-silicon thin film transistors (hereinafter referred to as “p-Si TFTS”) are more advantageous than amorphous silicon thin film transistors (hereinafeter referred to as “a-Si TFTs”) because they have a larger mobility and a higher driving ability. Therefore, the p-Si TFTs allow implementation of LCDs with high performance, in which, along with pixel portions, peripheral driving circuits can also be integrated on the same substrate.
In a p-Si TFT, so as to form source and drain regions in the p-Si film functioning as an active layer, the p-Si film is subjected to ion doping followed by a thermal processing for activation.
A method of manufacturing a TFT according to a related art will be described. FIG. 1 is a cross section of a TFT fabricated by a TFT manufacturing method according to a related art.
Referring to FIG. 1, a first gate insulating film 13 comprising an SiO2 film and a second gate insulating film 14 comprising an SiN film disposed thereon are formed over the entire surface of a substrate 10 so as to include a p-Si film 12.
In FIGS. 2A to 2D, cross sections of a TFT are depicted to illustrate the TFT manufacturing process steps according to the related art.
Step 1 (FIG. 2A):
On an insulating substrate 10 comprising a quartz glass, non-alkali glass or the like, an SiO2 film 11 serving as an insulating protective film is formed by the plasma CVD method, and an a-Si film 12 is formed on the SiO2 film 11 using plasma CVD method. Then, the a-Si film 12 is subjected to annealing by scanning to irradiate the surface thereof with an excimer laser such that the a-Si film 12 is molten and recrystallized to a p-Si film 12, which is then etched into an island shape functioning as an active layer.
Step 2 (FIG. 2B):
The first gate insulating film 13 comprising an SiO2 film and the second gate insulating film 14 comprising an SiN film are stacked over the entire surface of the p-Si film 12 by the CVD method. A conductive material comprising a refractory metal such as chromium (Cr) or molybdenum (Mo) is then deposited on the SiN film 14 using a sputtering method so as to form a gate electrode 15 such that it superposes the semiconductor film 12 using photolithography and dry etching by the RIE method.
Thereafter, P- or N-type impurity ions 16 corresponding to the type of a transistor to be formed are doped into the p-Si film 12 except the region covered with the gate electrode 15 through the first and second gate insulating films 13 and 14, with the gate electrode 15 acting as a mask. This ion doping creates an intrinsic or substantially intrinsic region of the p-Si film 12 beneath the gate electrode 15.
Step 3 (FIG. 2C):
A resist 17 having a smaller width than the p-Si film 12 is formed so as to cover the gate electrode 15 and the second insulating film 14. Then, impurity ions 18 are doped into the p-Si film 12 to form LDD (Lightly Doped Drain) regions 12LD having a low density of doped ions, source 12s and drain 12d having a high density of doped ions.
Thus, in the p-Si film 12, a region located right beneath the gate electrode 15 corresponds to a channel 12c, whereas regions located on both sides of the gate electrode 15 correspond to the source 12s and the drain 12d, respectively.
Step 4 (FIG. 2D):
subsequent to removal of the resist 17, an SiN film 19 and an SiO2 film 20 are sequentially stacked on the entire surface of the substrate 10 including the p-Si film 12 by the plasma CVD method, to form an interlayer insulating film comprising two films, namely the SiN film 19 and the SiO2 film 20.
After forming the SiN film 19 and the SiO2 film 20, first contact holes 30 are formed through the interlayer insulating film at positions corresponding to the source 12s and the drain 12d, respectively, so as to reach the p-Si film 12. Then, a source electrode 21 and a drain electrode 22 comprising aluminum or the like are formed in these first contact holes 30, respectively. Further, a planarization layer 23 comprising an organic resin or the like is deposited over these electrodes. Another contact hole 32 is then formed at a position of the planarization layer 23 corresponding to the source electrode 21, into which an ITO, a transparent electrode material, is deposited and patterned to form a pixel electrode 24.
While the TFT employing a p-Si film is advantageous due to its high mobility or the like as already described, the p-Si film has many crystalline defects at the grain boundaries and therefore electrons moving in the film tend to be easily trapped. It is particularly undesirable to have such crystalline defects in the channel region in a TFT. Therefore, it has been proposed that hydrogen be introduced in the film so as to terminate dangling bonds existing in these defects. In order to introduce hydrogen into the film, a method is known in which an SiN film containing a great number of hydrogen atoms is heated together with the p-Si film such that the hydrogen ions are transferred from the SiN film to the p-Si film. In this case, it is preferable that the SiN film and the p-Si film be located as close to each other as possible so as to supply the hydrogen (H) atoms in the SiN film to the p-Si film by heating. However, if the p-Si film and the SiN film are directly in contact with each other, the threshold values of the TFT employing such p-Si film vary due to predetermined charges generated in the SiN film. For this reason, in the above-mentioned top-gate type TFT, the SiN film 14 cannot be provided, as a gate insulating film, directly on the p-Si film 12, but the SiN film 14 must be formed on the SiO2 film 13 disposed on the p-Si film 12, resulting in a structure employing two gate insulating films, as shown in FIGS. 1, and 2A to 2D.
However, in a case where the gate insulating films comprise a sequence of two layers, namely the SiO2 film 13 and the SiN film 14 in the above-mentioned top-gate type TFT, the acceleration energy must be increased when doping ions into the semiconductor film so as to reach the p-Si film 12 through these two-layered gate insulating films. For example, phosphorus (P) ions must be doped with an acceleration energy of 100 keV or more. This may increase the power consumption of a doping apparatus.
Further, when the acceleration energy is increased for ion doping, the temperature of the substrate rises to as high as approximately 200° C. Such a high temperature deteriorates the resist 17 covering the gate electrode 15 and the LDD regions, which results in distortion in the periphery of the resist or makes the resist 17 difficult to peel off when removing it after ion doping.